Current-mode Multiple-input Max Circuit

A CMOS continuous time current-mode circuit which provides the maximum of n analog inputs is presented. This structure exhibits a O(n) complexity, and allows high precision and speed with small area and very low power dissipation. Its operation is discussed and illustrated with simulation results. INTRODUCTION Multiple-input Max/Min circuits are basic building blocks in many advanced computational systems, such as fuzzy or artificial neural networks. Solutions have been reported where the physical variable carrying on the information is either current or voltage. Hardware implementations which take voltages as inputs are generally based on operational amplifiers that means complex circuit blocks. More promising for VLSI are currentbased implementations, which fall into one of four approaches: a) cascaded realizations of two-input operators [1], which tend to introduce large delays when the number of inputs increases; b) circuits of O(n2) complexity with positive feedback [2]; c) structures with a negative feedback loop which require the introduction of a dominant pole to avoid stability problems [3]; and d) structures taking advantage of that a MOS transistor conducts the maximum current for a given gate to source voltage when it operates in saturation [5]. Although the circuit structure reported in [5] seems to exhibit a superior performance compared to other current-mode counterparts, it requires the use of 5n+1 transistors to implement an n-input Max operator. This letter aims to present another hardware realization of multi-input Max based on the same principle as the one in [5]. However, we exploit this idea in a different way to provide a circuit structure requiring only 3n+1 transistors for implementing the same function, yet providing better performance in terms of speed, area and power dissipation. CIRCUIT DESCRIPTION AND OPERATION Winner-take-all circuits have been reported [6-7] based on the interconnection of the simple two-transistor current-controlled current conveyor show in Figure 1. The result of the competition of some of these cells connected by the gate of transistors M, is a shared gate voltage corresponding to the saturation value imposed by the maximum input current, Imax. To convert a WTA into a current-mode MAX operator, we only need a simple transconductor such as a transistor in saturation to recover Imax from this shared voltage. The drawback is a very low output resistance, so that cascoded or regulated stages have to be used to improve accuracy, as done in [5]. Transistor T has been used as a voltage follower to cause the competition which determines the winner cell. However, the need of cascode stages, as well as the bias current Iss, can be eliminated if the dual role of the basic current conveyor cell in Figure 1 is exploited. The circuit we propose (shown in Figure 2) takes advantage of another feature, which is that the winner transistor Tj transfers the current Iss from a low impedance to a high impedance node. A diode-connected transistor in place of source Iss forces the current to be the winner Iin, that is Imax. Consequently, in an array of these competitive cells, the transistor Tj of the winner cell replicates the maximum input current to a high impedance output node (the other Ti, i≠j are off because their corresponding Mi operate in linear region). The resulting circuit may be seen as the connection of Wilson current mirrors which share their output diode-connected transistor. To avoid DC matching errors due to the asymmetrical biasing of a Wilson mirror, the design is optimized by using improved Wilson mirrors. The circuit is operational with transistors Mi working in either strong or weak inversion. Thus allowing current ranges as low as some nA (the limit is imposed by offsets of a few pA). On the other hand, the maximum input current is limited by the voltage drops at the input and/or output of the Wilson mirror cell. This structure is simpler than that reported in [5], achieving the same precision. In addition, since only the winner cell is conducting, the power dissipation of our proposed scheme is very much lower (∑i=1IiVDD for a N-input operator, instead of ∑i=1IiVDD+(1+N)Imax for that in [5]). The precision achieved has to be analysed from two points of view: accuracy in replicating Imax and ability to distinguish current levels. Regarding the first point, the precision of the proposed operator is that of an improved Wilson mirror. The limitation is, then, imposed by systematic and random errors typical of current mirrors. The systematic error, mainly due to the finite output resistance is very low [8] and random errors can be minimized if large transistor areas and currents are employed [9]. Therefore, accuracies of 8 bits can be expected. According to the second point, this circuit allows very high resolutions. This can be explained from the small signal model of the two-transistor cell in Figure 1. The differential gain between the currents through transistors M and T is ∆I(T)=gmTvgT=∆I(M)gmT/gdsM, with gmT representing the transconductance of transistor T and gdsM the output conductance of transistor M. In weak inversion, the constant, high value of gmT/gdsM allows resolutions in the range of pA. In strong inversion, gmT/ gdsM is proportional to (WL/I)1/2, so that large transistor areas or low currents are preferred to optimize resolution. The simplicity of our circuit is responsible for its high speed operation. There are not global feedback loops, only the voltage in the shared node is locally fed back. Dynamics of our circuit is similar to that of the improved Wilson mirror, as also happens to the circuit in [5]. Both circuits operate at high frecuencies but presents an overshoot in the time domain, whose underdamping coefficient is proportional to gm/C, being C the total capacitance in the gate of the output diode connected transistor. Since C is equal to (1+n)Cgs in our case instead of been (1+2n)Cgs as in the case for [5], thus the new circuit settles faster. SIMULATION RESULTS To illustrate the above analysis, the performance of the circuit has been simulated using Hspice. Level-6 MOS model parameters provided by ES2 for a typical 1.6μm CMOS process have been used in all simulation runs. Nmos transistors sizes of W/L=4mm/2mm have been chosen. Figure 3 shows the DC characteristics of a two-input operator with an input current (I1) continuously changing and the other (I2) changing in steps of 1mA. The transient response of a 3-input operator, which has been simulated taking into account transistors areas, is shown in Figure 4. The obtained delays are lower than 100 nanoseconds. SUMMARY AND CONCLUSIONS We have presented a very simple current-mode multiple-input maximum circuit. Its features of high speed, small area, low power dissipation and reasonable degree of precision make it quite suitable as a building block in computational or signal processing systems.